1. Field of the Present Invention
The present invention relates to a semiconductor device including insulated gate field effect transistors, referred to as “MIS transistors” hereinafter, as it components, and particularly to a configuration for reducing power consumption in a semiconductor device having miniaturized CMOS transistors (P- and N-channel MIS transistors). More particularly, the present invention relates to a structure for suppressing a gate tunnel current of a miniaturized MIS transistor.
2. Description of the Background Art
In a CMOS semiconductor device, as the size of MIS transistors is reduced, an operation power supply voltage is lowered for ensuring reliability of the transistors and reducing power consumption. For reducing the sizes of MIS transistors in accordance with lowering of the operation power supply voltage, values of various transistor parameters are reduced according to a certain scaling rule. According to the scaling rule, it is necessary to reduce a thickness Tox of a gate insulating film of the MIS transistor, and it is also necessary to reduce an absolute value Vth of a threshold voltage. However, it is difficult to reduce the absolute value of the threshold voltage according to the scaling rule. The threshold voltage is defined as a gate-source voltage, which causes a predetermined drain current under application of a predetermined drain voltage. If absolute value Vth of the threshold voltage is small, a weak inversion layer is formed in a channel region even with a gate-source voltage Vgs being 0 V, and a sub-threshold leak current, referred to as an “off-leak current” hereinafter, flows through this inversion layer.
Therefore, such a problem occurs that the off-leak current increases to increase the standby current in a standby cycle during which MIS transistors are off. Particularly, in a semiconductor device for use in a battery-powered equipment such as a portable equipment, it is greatly required to reduce the off-leak current in view of a lifetime of the battery.
For reducing the off-leak current, absolute value Vth of the threshold voltage can simply be increased. In this case, however, reduction of the operation power supply voltage cannot achieve an intended effect, and fast operation cannot be ensured. Thus, an MT-CMOS (Multi-Threshold CMOS) structure has been proposed for reducing the off-leak current in the standby cycle and for ensuring fast operation.
FIG. 104 shows, by way of example, a structure of an MT-CMOS circuit in the prior art. In the structure shown in FIG. 104, five inverter circuits IV0-IV4 are cascaded. For these inverter circuits IV0-IV4, there are arranged a main power supply line MVL coupled to a power supply node, a sub-power supply line SVL coupled to main power supply line MVL via a switching transistor SWP, a main ground line MGL coupled to a ground node, and a sub-ground line SGL coupled to main ground line MGL via a switching transistor SWN.
Inverter circuits IV0-IV4 each have a structure of a CMOS inverter, and include P-channel MIS transistors P0-P4 and N-channel MIS transistors N0-N4, respectively. This MT-CMOS circuit has a standby cycle in a standby state and an active cycle in which an input signal changes actually. In the standby cycle, input signal IN is fixed to L-level, and switching transistors SWP and SWN are kept in the off state in response to control signals/φ and φ, respectively. Each of switching transistors SWP and SWN has a threshold voltage relatively large (medium) in absolute value, M-Th. Each of MIS transistors P0-P4 and N0-N4 of inverter circuits IV0-IV4 has a threshold voltage of a small absolute value, L-Th.
Depending on a logical level of an input signal IN in the standby cycle, a source of each MIS transistor, which is on in the standby cycle, is connected to main power supply line MVL or main ground line MGL. More specifically, sources of MIS transistors P0, P2 and P4 are connected to main power supply line MVL, and sources of MIS transistors N1 and N3 are connected to main ground line MGL. A source of each MIS transistor, which is off in the standby cycle, is connected to sub-power supply line SVL or sub-ground line SGL. More specifically, sources of MIS transistors P1 and P3 are connected to sub-power supply line SVL, and sources of MIS transistors N0, N2 and N4 are connected to sub-ground line SGL. Now, an operation of the MT-CMOS circuit shown in FIG. 104 will now be described with reference to a signal waveform diagram of FIG. 105.
During the standby cycle, input signal IN is at L-level, and control signals φ and /φ are at L- and H-levels, respectively. In this state, switching transistors SWP and SWN are off. Switching transistor SWP is an M-Vth transistor, and the off-leak current thereof in the standby state cycle is small.
In inverter circuits IV0-IV4, MIS transistors P0, P2 and P4 are on, and therefore do not cause a sub-threshold leak (off-leak) current. Meanwhile, MIS transistors P1 and P3 are off, and cause an off-leak current from sub-power supply line SVL. The off-leak currents flowing through MIS transistors P1 and P3 flow to main ground line MGL through MIS transistors N1 and N3 in the on state, respectively. However, the off-leak current flowing through MIS transistors P1 and P3 depends in magnitude on the off-leak current flowing through switching transistor SWP. Therefore, the voltage level of sub-power supply line SVL reaches an equilibrium state where the off-leak current flowing through switching transistor SWP is balanced with the sum of off-leak currents flowing through MIS transistors P1 and P3. Due to the current flow, the voltage level of sub-power supply line SVL is lower than power supply voltage VCC, and MIS transistors P1 and P3 enters such a state that the gate to source thereof is reverse-biased, and therefore enters a deeper off state. Accordingly, MIS transistors P1 and P3 can have the off-leak currents sufficiently reduced.
Likewise, off-leak currents flow through MIS transistors N0, N2 and N4. These off-leak currents flowing through MIS transistors N0, N2 and N4 depend in magnitude on the off-leak current flowing through switching transistor SWN. Switching transistor SWN is an M-Vth transistor, and has a sufficiently small off-leak current so that the off-leak currents of MIS transistors N0, N2 and N4 can be sufficiently suppressed.
In the above case, the voltage level of sub-ground line SGL reaches an equilibrium state where the sum of off-leak currents flowing through MIS transistors N0, N2 and N4 are balanced with the off-leak current flowing through switching transistor SWN, and therefore is higher than ground voltage GND. In this case, each of MIS transistors N0, N2 and N4 enters such a state that the gate to source thereof is reverse-biased, and therefore enters a deeper off state. Accordingly, MIS transistors N0, N2 and N4 can have the off-leak current sufficiently suppressed.
In the active cycle for actually performing an operation, control signals φ and /φ are set to H- and L-levels, respectively, and switching transistors SWP and SWN are turned off. Responsively, sub-power supply line SVL is connected to main power supply line MVL, and sub-ground line SGL is connected to main ground line MGL. Inverter circuits IV0-IV4 include L-Vth transistors as components, and therefore, rapidly change their output signals in accordance with input signal IN.
As shown in FIG. 104, the power supply line differs in impedance value depending on the standby cycle and the active cycle. Thereby, even with the L-Vth transistors employed as its components, the off-leak current can be sufficiently suppressed in the standby cycle, while ensuring fast operation performance in the active cycle. Accordingly, a CMOS circuit capable of fast operation with low power consumption can be implemented.
Various parameters such as sizes of the MIS transistors are reduced according to a certain scaling rule. The scaling rule stands on the premise that the gate length of the MIS transistor and the thickness of the gate insulating film thereof are reduced at the same scaling ratio. For example, an MIS transistor having a gate length of 0.25 μm (micrometers) generally has a gate insulating film of 5 nm (nanometers) in thickness, and therefore an MIS transistor having a gate length of about 0.1 μm has a gate insulating film from about 2.0 to about 2.5 nm in thickness. In the case where the thickness of gate insulating film is reduced in accordance with lowering of the operation power supply voltage and is reduced to about 3 nm in accordance with the condition that the power supply voltage is 1.5 V or lower, for example, a tunnel current flows through the gate insulating film of MIS transistor in the on state, resulting in a problem of increase in power supply current of the transistor in the on state.
FIGS. 106A-106C schematically show energy bands of the MIS transistor, with the gate being a metal gate. Normally, in the MIS structure, a gate is formed of polycrystalline silicon doped with impurities and has properties as a semiconductor. For simplicity reason, however, it is here assumed that the gate is made of a metal. The semiconductor substrate region is of the P-type substrate (layer).
As shown in FIG. 106A, it is now assumed that a negative voltage is applied on the gate. In this state, holes present in the P-type substrate are pulled toward the interface between the substrate and the insulating film. Thereby, the energy band of the P-type substrate is bent upward at the interface between the insulating film and the P-type substrate, and a valence band Ev approaches a Fermi level EF. A conduction band Ec is bent upward at the vicinity of this interface. In this case of application of the negative voltage, Fermi level EF of the gate (corresponding to conduction band Ec in the case of a polycrystalline silicon gate) also rises. In this state, the density of majority carriers (holes) on the interface is higher than that in the inner portion. This state is called an accumulated state. In this state, the conduction band Ec is bent upward, and a barrier against electrons is high so that the tunneling current through the gate insulating film does not flow.
Where a low positive voltage is applied to the gate as shown in FIG. 106B, the Fermi level (conduction band) of the gate lowers so that conduction band Ec and valence band Ev are bent downward in the P-type substrate region at the interface with the insulating film. In this state, holes have been located away from the interface to the gate insulating film so that depletion of majority carriers occurs, and Fermi level EF on the interface is located substantially in the center of the band. This state, where a majority carrier is not present, is called a depletion state. In this depletion state, a carrier is not present on the interface, and a tunnel current does not occur.
When a further high positive voltage is applied as shown in FIG. 106C, Fermi level EF of the gate further lowers, and the band bending at the vicinity of the interface occurs to a larger extent. Consequently, Fermi level EF of the gate exceeds the intermediate value of energy gap Eg at the vicinity of the interface, and electrons which are minority carries are accumulated. This state is called an inverted state because the conduction type of the interface is inverted with respect to that of the interior. This state corresponds to the state where a channel is formed in the MIS transistor. If the gate insulating film has a thickness δ of, e.g., 3 nm in this state, electrons which are minority carriers flow into the gate through a tunneling phenomenon. Thus, the tunnel current directly flows into the gate from the channel region in the MIS transistor having the channel formed and thus conductive. This tunnel current is called a (direct) gate tunnel current. Similar behaviors occur in a structure having an N-type substrate region, except for that a voltage applied to the gate has the opposite polarity and that the energy band bends in the opposite direction.
In MIS transistor, if the thickness of the gate insulating film is reduced, e.g., to 3 nm, a direct gate current flows from the channel region to the gate. Consequently, the MT-CMOS circuit such as that shown in FIG. 104 accompanies the following problem. In the standby cycle, a tunnel current flows from the channel region to the gate in an on state MIS transistor, and through-current finally flows from the power supply node to the ground node so that the current consumption in the standby cycle increases.
FIG. 107 shows a path of a tunnel current in the MT-CMOS circuit shown in FIG. 104 in the standby cycle.
FIG. 107 shows a structure of a portion including inverter circuits IV1 and IV2. In inverter circuit IV1, MIS transistor N1 has a source and a back gate connected together to main ground line MGL, and MIS transistor P1 has a source connected to a sub-power supply line (not shown). In inverter circuit IV2, MIS transistor P2 has a back gate and a source connected together to main power supply line MVL, and MIS transistor N2 has a source connected to a sub-ground line (not shown).
In the standby cycle, inverter circuit IV1 is supplied with a signal at H-level. Therefore, the output signal of inverter circuit IV1 is at L-level or the level of ground voltage GND in the standby cycle, and MIS transistor P2 in inverter circuit IV2 is on. In MIS transistor P2, a tunneling current It flows from the substrate region to the gate, and further flows to main ground line MGL through MIS transistor N1. As indicated by broken line in FIG. 107, the gate tunnel current of MIS transistor P2 causes a through current flowing from main power supply line MVL to main ground line MGL.
FIG. 108 shows a structure of a portion including inverter circuits IV2 and IV3 of the MT-CMOS circuit shown in FIG. 104. In the standby cycle, inverter circuit IV2 is supplied with a signal at L-level. The sources of MIS transistors P2 and N3 are connected to main power supply line MVL and main ground line MGL, respectively, while the sources of MIS transistors N2 and P3 are connected to the sub-ground line and sub-power supply line (both not shown in FIG. 108), respectively. In this state in the standby cycle, MIS transistor P2 is on, and supplies a current to the gate of MIS transistor N3 from main power supply line MVL.
MIS transistor N3 is on, and therefore gate tunnel current It flows through MIS transistor N3 (through the source region and the back gate region) to main ground line MGL. When the back gate of MIS transistor N3 is biased to a voltage level different from ground voltage GND, gate tunnel current It of MIS transistor N3 flows from this channel region through the source region. In this case, therefore, gate tunnel current It likewise causes a though current flowing from main power supply line MVL to main ground line MGL.
This gate tunnel current is nearly equal to the off-leak current when the gate oxide film has a thickness of about 3 nm or less. If the gate oxide film has a thickness smaller than about 3 nm, the gate tunnel current exceeds the off-leak current. Therefore, in the case where the operating power supply voltage is lowered and the thickness of gate insulating film is reduced according to the scaling rule, this gate tunnel current cannot be neglected and causes a problem of increase in current consumption in the standby cycle.
A gate tunnel current J approximately satisfies the relationship expressed by the following formula:J˜E·exp [−Tox·A·√φ],where φ represents a height of a barrier at the interface with the gate insulating film, and is approximately expressed by a difference between the Fermi level and the surface potential φs at the interface, A is a constant depending on an impurity concentration (an effective mass of an electron) of the semiconductor substrate in the channel region, and E represents an electric field applied to the gate insulating film. The barrier Height φ is a function of a dielectric constant εi and thickness Tox of the gate insulating film. Therefore, if a tunnel current starts to flow at the gate oxide film thickness of 3 nm with the gate insulating film formed of silicon oxide, a gate tunnel current likewise flows through the gate insulating film, which provides a barrier equal to that by the silicon oxide film of 3 nm in thickness. As the gate insulating film, there is a silicon nitride oxide film, other than the silicon oxide film (silicon dioxide film).
As described above, with the miniaturized transistors as components, there arises a problem that the gate tunnel current of the MIS transistor becomes substantially equal to or larger than the off-leak current in the standby, and the current consumption in the standby cycle cannot be reduced.